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description the a4403 is a buck converter that uses valley current-mode control. this control scheme allows very short switch on-times to be achieved, making it ideal for applications that require high switching frequencies combined with high input voltages and low output voltages. low cost is accomplished through high switching frequencies of up to 2 mhz, allowing smaller and lower value inductors and capacitors. in addition, minimal external components are required through high levels of integration. optimal drive circuits are utilized to minimize switching losses. the switching frequency is maintained constant, as the on-time is modulated by the input voltage. this feed-forward control ensures excellent line correction. the on-time is set by an external resistor pulled-up to the input supply. when power is initially applied and the device is enabled, a user-configurable soft-start function occurs to minimize inrush current and to prevent output overshoot. internal housekeeping and bootstrap supplies are provided which only require the addition of one small ceramic capacitor. a top-off charge pump is also provide to ensure correct operation at light loads. internal diagnostics provide comprehensive protection against overcurrents, input undervoltages, and overtemperatures. the device package is a 16-contact, 4 mm 4 mm, 0.75 mm nominal overall height qfn, with exposed pad for enhanced thermal dissipation. it is lead (pb) free, with 100% matte tin leadframe plating. 4403-ds, rev. 1 features and benefits ? extremely fast load-transient response with minimal output voltage delta ? achieves high step-down ratios with on-times < 50 ns ? user-configurable on-time, achieving switching frequencies up to 2 mhz ? minimal external components required ? optimized for low value filter capacitors and inductors ? wide input voltage range: 9 to 46 v ? output current: 3 a ? low standby current <100 a ? supplied in thermally-enhanced qfn package valley current mode control buck converter applications: a4403 package 16-contact qfn (suffix eu): ? printers, scanners ? cable, dsl modems/routers ? network and telecom ? industrial control ? distributed power systems ? set top box ? high power led supply ? battery chargers ? gps / infotainment 4 mm 4 mm 0.75 mm gnd l d1 1 6.3 h lx fb vin 5.0 v 3 a 6.3 v isen sgnd v out a 4403 ton 22 nf r1 100 k c1 2.2 f 100 v 50 m ss dis r3 750 r6 3.92 k r5 c2 47 nf c5 10 f c3 6.3 v 10 f c4 boot v in 9 to 46 v all capacitors are x5r or x7r ceramic resistors r3 and r4 should be surface mount, low inductance type, rated at 250 mw at 70c typical application diagram efficiency versus output current v in = 42 v 60.00 65.00 70.00 75.00 80.00 85.00 90.00 0123 output current (a) efficiency (%) 5 v 3.3 v
valley current mode control buck converter a4403 2 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com absolute maximum ratings ( reference to gnd) characteristic symbol notes rating units vin pin supply voltage v in ?0.3 to 50 v lx pin switching node voltage v lx ?1 to 50 v isen pin current sense voltage v isen ?1.0 to 0.5 v dis pin disable voltage v dis ?0.3 to 7 v ton pin on-time voltage v ton ?0.3 to 50 v operating ambient temperature t a range g ?40 to 105 oc maximum junction temperature t j (max) 150 oc storage temperature t stg ?55 to 150 oc selection guide part number packing package a4403geu-t 92 pieces per tube 16-contact 4 mm 4 mm qfn with exposed thermal pad a4403geutr-t 1500 pieces per 7-in. reel thermal characteristics may require derating at maximum conditions, see application information characteristic symbol test conditions* value units package thermal resistance, junction to ambient r ja on 4-layer pcb based on jedec standard 36 oc/w package thermal resistance, junction to pad r jp on 4-layer pcb based on jedec standard 2 oc/w *additional thermal information available on the allegro website. recommended operating conditions characteristic symbol conditions min. typ. max. units supply voltage v in 9 ? 46 v switching node v lx ?0.7 ? 46 v switching frequency range f sw continuous conduction mode 0.45 ? 2 mhz operating ambient temperature t a ?40 ? 105 oc junction temperature t j ?40 ? 125 oc
valley current mode control buck converter a4403 3 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com reg ref +80 mv reg ref v out control logic on timer regulator comparator off timer soft-start driver linear regulator fault vin uvlo tsd linear ok vin dis gnd ton boot lx isen fb v in 9 to 44.1 v v in ss sleep circuit sgnd switch closed = on nc amplifier overvoltage comparator c1 2.2 f c4 c2 10 f c3 10 f l1 4.7 h c5 d1 r3 r6 r5 100 m 3.3 v 3 a blank top-off charge pump c6 10 nf 750 2.37 k 47 nf 22 nf r4 100 m r1 68 k r2 not fitted switching frequency = 1 mhz all capacitors are x5r or x7r ceramic resistors r3 and r4 should be surface mount, low inductance type, rated at 250 mw at 70c c6 is an optional speed-up capacitor, to improve the transient response + ? + ? + ? functional block diagram pin-out diagram terminal list table number name function 1 vin input supply 2, 7, 13, 14, 15, 16 nc no connection; tie to gnd 3 ton terminal for on-time setting with external resistor 4 ss terminal for soft-start setting with external capacitor 5 fb feedback terminal 6 gnd ground terminal 8 isen current sense input 9 sgnd current sense ground reference 10 dis disable logic input; active high 11 boot bootstrap supply node 12 lx switch node ?pad exposed thermal pad; connect to ground plane (gnd) by through-hole vias 12 11 10 9 1 2 3 4 5 6 7 8 16 15 14 13 nc nc nc nc fb gnd nc isen lx boot dis sgnd pad vin nc ton ss (top view)
valley current mode control buck converter a4403 4 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics 1 valid at t j = 25c, v in = 9 to 46 v, unless otherwise noted characteristic symbol conditions min. typ. max. units general v in quiescent current i vinoff dis = high, vin = 46 v ? ? 100 a i vinon dis = low, vin = 46 v, i load = 1 ma ? 4.3 5.5 ma feedback voltage v fb t j = 25c 0.792 0.8 0.808 v feedback input bias current i bias ?400 ?100 100 na output voltage tolerance 2 ? v out i load = 1 ma to 3 a ?2.5 ? 2.5 % on-time tolerance ? t on based on selected value ?15 ? 15 % minimum on-time period t on(min) ? 50 60 ns minimum off-time period t off(min) ? ? 350 ns buck switch on-resistance r ds(on) t j = 25c, i load = 3 a ? 350 ? m t j = 125c, i load = 3 a ? 550 ? m current limit threshold i lim valley current in external sense resistors = 50 m 3.0 3.6 4.2 a soft start current source i ss 5 10 15 a input dis input voltage threshold v dis device enabled ? ? 1 v dis open-circuit voltage v disoc device disabled 2 ? 7 v dis input current i in dis = 0 v ?10 ? ?1 a protection fb overvoltage shutdown v fbov ? 0.88 ? v vin undervoltage shutdown threshold v inuv voltage rising 6.4 ? 7.5 v vin undervoltage shutdown hysteresis v inuv(hys) 0.7 ? 1.1 v overtemperature shutdown threshold t jtsd temperature rising ? 165 ? c overtemperature shutdown hysteresis t jtsd(hys) recovery = t jtsd ? t jtsd(hys) ? 15 ? c 1 specifications over the junction temperature range of ?40c to 125c are assured by design and characterization. 2 average value of v out relative to target voltage. note that the tolerance effects of the feedback resistors are not taken into account. this figure does include the feedback voltage tolerance.
valley current mode control buck converter a4403 5 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com basic operation the a4403 is a buck converter that utilizes valley current-mode control. the on-time is set by the amount of current that flows into the ton pin. this is determined by the value of the ton resistors chosen (r1 and r2 in the functional block diagram) and the magnitude of the input voltage, v in . under a specific set of conditions, an on-time can be set that then dictates the switching frequency. this switching frequency remains reasonably constant throughout load and line conditions as the on-time varies inversely with the input voltage. the switch on-time and switching frequency section provides more details on this subject. at the beginning of the switching cycle, the buck switch is turned on for a fixed period that is determined by the current flowing into ton. once the current comparator trips, a one-shot mono- stable, the on timer, is reset, turning off the switch. the current through the inductor then decays. this current is sensed through the external sense resistors (r3 and r4), and then compared against the current-demand signal. the current-demand signal is generated by comparing the output voltage against an accurate bandgap reference. after the current through the sense resistors decreases to the valley of the current-demand signal, the on timer is set to turn the buck switch back on again and the cycle is repeated. under light load conditions, the converter automatically operates in pulse frequency modulation (pfm) mode to maintain regu- lation. this mode of operation ensures optimum efficiency as switching losses are reduced. overcurrent protection the converter utilizes pulse-by-pulse valley current limiting, which operates when the current through the sense resistors, r3 and r4 (set for 50 m by two 100 m resistors in parallel), increases above 3.6 a typical at the valley point. the corresponding sense voltage (at the isen pin) that cre- ates a current limiting condition is 180 mv typical. it is possible, by careful selection of the sense resistors, to reduce the current limit for systems with maximum loads of less than 3 a. during an overload condition, the switch is turned on for the period determined by the constant on-time circuitry. the switch off-time is extended until the current decays to the current limit value of 3.6 a typical (which corresponds to a sense voltage of 180 mv). the switch is then turned on again. because no slope compensation is required in this control scheme, the current limit is maintained at a reasonably constant level across the input voltage range. figure 1 illustrates how the current is limited during an overload condition. the current decay (period with switch off) is propor- tional to the output voltage. as the overload is increased, the out- put voltage tends to decrease and the switching period increases. output voltage selection the output voltage of the converter is set by selecting the appropriate feedback resistors, using the following formula: r 5 r 6 =, ? ? ? ? ? ? ? ? v fb v out ? 1 (1) where (refering to the functional block diagram): r 6 has a value between 750 and 12 k (r6 connected between the gnd and fb pins), r 5 is the dependent value (r5 connected between the output rail and the fb pin), v out is the user-configured output regulator voltage, and v fb is the reference voltage. the tolerance of the feedback resistors influences the voltage set- point. it is therefore important to consider the tolerance selection when targeting an overall regulation figure. functional description current limit level inductor current operating at maximum load maximum load constant on-time constant on-time current current time constant period current limit level inductor current operating in a ?soft? overload overload time extended period figure 1. current limiting during overload
valley current mode control buck converter a4403 6 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com in general, the feedback resistors should have the lowest resis- tance possible, to minimize any noise pick-up effects and to minimize voltage offsets on the output caused by the bias current, i bias , flowing out of the fb node into r6. reducing the feedback resistances does introduce another loading effect on the output, which has an effect on the standby current. it should be noted that a minimum load of 1 ma is required (see the light load operation section). this may be provided by the feedback resistors. for example, if r6 = 750 , this guarantees a 1 ma load current. disable the converter is enabled by pulling the dis pin low. once enabled, the output converter is started-up under the control of the soft-start routine. to disable the converter, the dis pin can simply be disconnected (open circuit). soft start a soft-start routine is initiated when: dis = 0, no thermal shutdown exists, and v in and the internal housekeeping supplies are above the minimum values. note that an overcurrent event does not initiate a soft start, unless the converter is recover- ing from a thermal shutdown condition. the soft-start routine controls the rate of rise of the reference voltage, which in turn controls the output voltage. this function minimizes the amount of inrush current drawn from vin and potential voltage overshoot on the output rail, vout. the soft-start period, t ss , is set by an internal current source that charges the external capacitor (c5) connected to the ss pin. control by the soft-start routine is completed when the ss pin reaches 0.8 v. the duration of t ss is set by selecting the appro- priate capacitance, according to the formula: t ss =. 10 10 ?6 c 5 0.8 (2) note: if the soft start function is not required for the application, a 220 k resistor should be connected between the ss pin and gnd. without soft start, or with a soft start period that is too rapid, coupled with a high load that is present during start-up, the converter may operate in current limit, placing maximum stress on the input circuit. assuming no load is drawn until the start-up process is complete, the current drawn from the input supply is determined by how quickly the output capacitors (c3 and c4) are charged. the out- put capacitors are charged according to the following formula: t charge =, i v in c out v out (3) where i vin is the input supply current. for example, if you limited i vin to 250 ma, and assumed v out = 5 v and c out = 20 f, the soft start time could be determined as: t charge == 0.25 a 20 f 5 v 400 s this means a soft-start duration greater than 400 s should be selected to ensure the inrush current is less than 250 ma. shutdown the converter is disabled in the event of either an overtemperature event, or an undervoltage on vin (v inuvr ) or on an internal housekeeping supply. as soon as any of the above faults have been removed and assuming dis = 0, the output voltage, v out , is brought-up under the control of the soft-start routine. output overvoltage protection in the event of an over- voltage condition appearing on the output rail, the fb terminal will also experience the overvoltage, scaled by the feedback resis- tors. if the fb terminal voltage rises above the nominal voltage by 10% (typical), the on-time of the buck switch will terminate and the switch will remain off until the fb voltage reduces to the correct v fb range. switch on-time and switching frequency the switch on-time effectively determines the operating frequency of the converter. the selection of the operating frequency is generally a trade-off between the size of the external passive components (inductor, and input and output capacitors) and switching losses. another consideration in selecting the switching frequency is to ensure that none of the on- or off-time limits are reached under extreme conditions. the minimum on-time occurs at maximum input voltage and minimum load. consider the following example. given: v in (max) = 46 v, v out = 5 v, f sw = 1 mhz, and: t on (min) = , ? ? ? ? ? ? ? ? v in + v f v out + v f f sw 1 (4) where v f is the voltage drop of the recirculation diode (d1) and sense resistors (r3 and r4).
valley current mode control buck converter a4403 7 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com then, the minimum on-time is: t on (min) 118 ns == ? ? ? ? ? ? ? ? 46 + 0.5 5 + 0.5 1 1 10 6 the specified minimum on-time, t on(min) , is 60 ns maximum, so there is reasonable margin in this case. the specified minimum off-time, t off(min) , 350 ns maximum, also has to be considered. the minimum off-time occurs at minimum input voltage and maximum load. as was shown in the minimum on-time calculation (equation 4), you have to exam- ine the extreme operating conditions to ensure adequate margin exists. the switch on-time, t on , is set by the current flowing into the ton pin. the current is determined by the input voltage, v in , and the resistor r1. the on-time can be found as: t on = . ? ? ? ? ? ? ? ? v in 2.05 10 10 r 1 + 10 10 ?9 (5) the switching frequency may be slightly modulated by load changes. the on-time is always constant for a given input voltage and across the load range. to compensate for any losses in the circuitry (for example, in the series switch and inductor, or in the voltage drop across the recirculation diode), the off-time, hence the switching frequency, has to be adjusted. this effect is most noticeable at low input voltages and high output currents. to calculate the actual switching frequency, the t on of equa- tion 5 can be used in conjunction with the transfer function of the converter: f sw = . ? ? ? ? ? ? ? ? v in + v f v out + v f t on 1 (6) an alternative approach to selecting the ton resistor (r1), to accomplish an approximate switching frequency is found in the following formula: r 1 = . f sw v out 2.05 10 10 (7) figure 2 illustrates a range of switching frequencies that can be achieved with various ton resistances and output voltages. top-off charge pump during light load operation, when operating in pfm mode, the top-off charge pump provides enough charge to drive the buck switch. light load operation to avoid the output voltage peak charg- ing due to leakage effects from the buck switch and the charge pump recirculation current, a minimum load of 1 ma must be applied to the output. the output feedback resistor network provides some loading. depending on the values selected, this network may provide all, or at least some, of the minimum loading requirement. control loop the process of closing the control loop for the a4403 has been greatly simplified through the integration of the compensation components into the device. the control loop bandwidth has been optimized for operation across the full input and output voltage range and for switching frequencies between 450 khz and 2 mhz. loop optimization is achieved with a 20 f ceramic capacitor placed across the output (vout to gnd) and a power inductor that achieves a peak to peak ripple current of around 720 ma. for example, for a 3.3 v output operating at a frequency of 1 mhz, the power inductor = 4.7 h. larger output capacitors can be used; however, this tends to decrease the bandwidth of the control loop. note that the output capacitance should not exceed 1000 f or be less than 10 f, as this may cause a loop instability to occur. 400 600 800 1000 1200 1400 1600 1800 2000 10 100 1000 resistor r1 (k ) switching frequency (khz) 0.8 v 1.5 v 3.3 v 5 v 12 v v out figure 2. switching frequencies versus ton resistor values, at various levels of v out
valley current mode control buck converter a4403 8 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com when the output voltage is set for 0.8 v, the typical bandwidth is 90 khz with a phase margin of 45 at full load. as the load is reduced, the bandwidth remains largely constant; however, the phase margin tends to reduce slightly because the output power pole is shifted down in frequency, introducing the phase lag sooner. at light loads, before pulse frequency modulation occurs, the phase margin reduces to approximately 40, which is reason- able given that it is the worst-case condition. note that when pulse frequency modulation occurs, the system no longer operates as a linear system, therefore, the control laws do not apply. when the output voltage is set for higher voltages, the dc gain is reduced by the resistor feedback network from the output. this effectively reduces the bandwidth of the control loop. an optional speed-up capacitor (c6) can be used in parallel with the feedback resistor (r5) to compensate for this effect. the addition of this capacitor introduces an additional zero which increases the gain and extends the bandwidth to maintain it in the region of 90 khz. the position of the zero depends on the values of r5 and c6. the following time constants should be used for various output voltages: output voltage (v) time constant ( ) 5 3.6 10 ?5 3.3 2.4 10 ?5 2.5 1.8 10 ?5 1.5 1.1 10 ?5 0.8 not required for example, assume a target output voltage of 5 v, and an r5 of 3.92 k to achieve that voltage. then c6 = 9.18 10 ?9 . the nearest commonly available value is 10 nf. for applications that require output voltages (v out ) other than what is defined above, the following formula should be used to calculate the time constant: = v out 7.2 10 ?6 , (8) inductor the main factor in selecting the inductance value is the ripple current. the ripple current affects the output voltage ripple and also has an effect on the current limit. because slope compensation is not used, the ripple current is not constrained by this factor. a good starting point in selecting the inductance for a given application is to specify a maximum peak-to-peak ripple current of about 25% of the maximum load. the equates to a ripple cur- rent of approximately 750 ma for a maximum load of 3 a. this often gives a good compromise between size, cost, and perfor- mance. the maximum peak to peak ripple current, i ripp , occurs at the maximum input voltage. therefore the duty cycle, d, should be found under these conditions: d (min) = , v out +v f v in (max) +v f (9) where v f is the forward voltage drop of the recirculation diode and the sense resistor. the required inductance can be found: l (min) d (min) = . i ripp v in ? v out f sw (min) 1 (10) note that the manufacturers inductance tolerance should also be taken into account. this value may be as high as 20%. in addition, because the control is dependant on the valley signal, it is important to consider the minimum peak to peak valley voltage that is developed across the sense resistor. the minimum peak to peak ripple current occurs at minimum input voltage. the peak to peak voltage is simply the peak to peak current multiplied by the sense resistor value. it is recommended that the peak to peak sense voltage should be greater than 25 mv. it is recommended that gapped ferrite solutions be used as opposed to powdered iron solutions. the latter exhibit relatively high core losses that can have a large impact on long term reli- ability. inductors are typically specified at two current levels: ? rms current. it is important to understand how the rms cur- rent level is specified, in terms of ambient temperature. some manufacturers quote an ambient only, whilst others quote a tem- perature that includes a self-temperature rise. for example, if an inductor is rated for 85c and includes a self-temperature rise of 25c at maximum load, then the inductor cannot be safely oper- ated beyond an ambient temperature of 60c at full load. the rms current can be assumed to be simply the maximum load
valley current mode control buck converter a4403 9 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com current, with perhaps some margin to allow for overloads, and so forth. ? saturation current. the worst case maximum peak current should not exceed the saturation current and indeed some mar- gin should be allowed. the maximum peak current can be found to ensure the saturation current level of the chosen inductor is not exceeded: i sat i load + = . i ripple 2 (11) it is important to ensure that, under worst-case conditions (mini- mum input voltage, maximum load current, minimum inductance, and minimum switching frequency), that the minimum current limit is not exceeded and in fact has some margin. the current limit is measured at the valley level. the maximum current at the valley is found from: i valley i load ? = . i ripple 2 (12) the minimum current limit threshold should be at least 20% above this level. recommended inductor manufacturers and ranges are: ? tayo yuden: nr6045 series ? sumida: cdr7d43mn series output capacitor in the interests of size, cost, and perfor- mance, this control architecture has been designed for ceramic capacitors. it is imperative that ceramic x5r or x7r capacitors are used. on no account should y5v, y5u, z5u, or similar types be used. when using ceramic capacitors, another important consider- ation is the e-field effects on the actual value of the capacitor. to minimize the effects of the capacitance being reduced with output voltage, it is recommended that the working voltage of the capacitor be considerably more than the set output voltage. check with the vendor to obtain this information. the output capacitor determines the output voltage ripple and is used to close the control loop. as outlined in the control loop section, the bandwidth has been optimized for an output capaci- tance of 20 f. if a particular application requires an extremely low output volt- age, the output capacitor can be increased. any increase will tend to reduce the bandwidth and therefore compromise the transient response performance. in general the output capacitance should not exceed 1000 f or be less than 10 f, as this may cause a loop instability to occur. the output ripple is largely determined by the output capacitance, and the effects of esr and esl can largely be ignored assum- ing good layout practice is observed. to help reduce the effects of esl it is a good idea to split the 20 f capacitance into two separate 10 f components. the output voltage ripple can be approximated to: v ripple , i ripple 8 f sw c out (13) where i ripple is as found in the inductor section. when using ceramic capacitors, due to the negligible heating effects of the esr, there is generally no need to consider the cur- rent carrying capability. also, the rms current flowing into the output capacitor is extremely low. input capacitor it is recommended that ceramic x5r or x7r capacitors be used, or at least that they be used in conjunction with some other capacitor technology; for example, aluminum electrolytic. note that the self-resonance of electrolytics tend to occur in the 100s of khz, therefore the effects of esl become apparent at switching frequencies in the region of 1 mhz. the value of the input capacitance determines the amount of ripple voltage that appears at the source terminals. if a system is designed correctly, the input capacitor should supply the switch- ing current minus the input average current during the on-time of the power switch. during the off-time of the power switch, the input capacitor is charged-up. the rms current that flows in the input capacitor can be found from: i rms 1 = , i out v out v in ? ? ? ? ? ? ? ? ? v out v in 1/2 (14) the amount of ripple voltage that appears across the input termi- nals depends on: the amount of charge removed during the switch on-time and the actual capacitor value. if a capacitor technology such as an electrolytic is used, then the effects of esr also have to be considered.
valley current mode control buck converter a4403 10 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the amount of capacitance required for a given ripple voltage can be found: c in = . i rms t on v ripple (15) as mentioned in the previous section, e-field biasing effects can reduce the actual capacitance and this should be taken into account when making the selection. again, there is generally no need to consider the heating effects of the rms current flowing through the esr of a ceramic capacitor. if an electrolytic device is used, then the ripple current rating should be considered. note that most manufacturers only consider the rms current rating at 100 khz. recirculation diode this diode (d1) conducts during the switch off-time. a schottky diode is recommended to minimize both the forward drop and switching losses. the worst-case dissipation occurs at maximum v in , when the duty cycle is at a minimum. the average current through the diode can be found: i diode(av) = i load (1 ? d (min)) . (16) the forward voltage drop, v f , can be found from the diode characteristics by using the actual load current (not the average current). the static power dissipation can be found: p stat = i diode(av) v f . (17) it is also important to take into account the thermal rating of the package, r ja , and the ambient temperature, to ensure that enough heatsinking is provided to maintain the diode junction temperature within the safe operating area for the device. to minimize the heating effects from the a4403 on the diode and vice-versa, it is recommended that the diode be mounted on the reverse side of the printed circuit board. sense resistor the sense resistor should be a surface mount package, with low inductance. on no account should a wire- wound or through hole package be used. to prevent potential mistriggering problems from occurring in noisy systems, it is recommended that an r-c filter be applied across the sense resis- tor, as shown in figure 3. the sense resistor value is selected depending on the maximum output load current. the typical sense voltage that causes a cur- rent limit is 180 mv. so, for example, a 50 m value would be appropriate for a maximum load of 3 a, as it allows for margin between maximum load and the current limit. a tolerance of up to 5% is acceptable. the power rating of the resistor has to be considered. the current flowing in the resistor is essentially the same as the current flow- ing through the recirculation diode, although the power dissipa- tion is worked out using the rms current. to a first approximation, the sense resistor dissipation can be worked out as: p sense = i load 2 (1 ? d (min)) r sense . (18) for a converter working with a load of 3 a, a very narrow duty cycle, and a sense resistor of 50 m , the power dissipation would be 450 mw. the optimal solution from a cost perspective is to use two 100 m , 1206-style resistors connected in parallel. each resistor is generally rated at 250 mw at 70c ambient. check the vendor datasheet to verify the maximum ambient at full power. when laying out the pcb, it is essential that the sense resistor connections, carrying the power current (see figure 3), are as short and wide as possible to minimize the effects of leakage inductance noise. in addition, the kelvin sense circuit connec- tions should be as close to the sense resistor pads as possible. figure 3. r-c filter added to the current sense circuit isen kelvin connection kelvin connection a4403 sgnd 47 r filter r sense power current 1 nf c filter
valley current mode control buck converter a4403 11 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com r filter and c filter (r7 and c7 in the typical application diagram) should be placed close to the a4403 pins. the ground sense should connect directly to the sgnd and not to the power ground. support components the bootstrap capacitor (c2) and soft- start capacitor (c5) should be ceramic x5r or x7r. thermal considerations to ensure the a4403 operates in the safe operating area, which effectively means restricting the junction temperature to less than 150c, several checks should be made. the general approach is to work out what thermal imped- ance, r ? ja , is required to maintain the junction temperature at a given level, for a particular power dissipation. (another factor worth considering is that other power dissipating components on the system pcb may influence the thermal performance of the a4403. for example, the power loss contribution from the recirculation diode and the sense resistor may cause the junction temperature of the a4403 to be higher than expected.) it should be noted that this process is usually an iterative one to achieve the optimum solution. the following steps can be used as a guideline for determining the r ? ja for a suitable thermal solution. : 1. estimate the maximum ambient temperature, t a (max) , of the application. 2. define the maximum junction temperature, t j (max). note that the absolute maximum is 150c. 3. determine the worst case power dissipation, p d (max). this will occur at maximum load and minimum v in . contributors are: (a) switch static losses estimate the maximum duty cycle: d (max) = , v out + v f v in (min) + v f (19) where v f is the forward voltage drop of the schottky diode (d1) and sense resistor (r2, r3) under the given load current. estimate the r ds(on) of the buck switch at the given junction temperature: r ds(on)tj r ds(on)25c 1 + = . ? ? ? ? ? ? ? ? 170 t j ? 25 (20) the static loss for each switch can be determined: p stat = i load 2 d (max) r ds(on)tj , (21) where i load is the load. (b) switch dynamic losses both the turn-on and the turn-off losses can be estimated: p dyn v in (min) 5 10 ?9 f sw 1.6 = , i load 2 (22) where f sw is the switching frequency. (c) diode capacitance turn-on loss at turn-on, an additional current spike flows into the switch, caus- ing a loss as follows: p diodecap = , c diode v in 2 f sw 2 (23) where c diode is the body capacitance of the schottky diode (d1). (d) control losses the control losses can be estimated as follows: p ctrl = i vinon v in , (24) where i vinon is the quiescent current with the converter enabled. (e) gate charge losses estimate the charge losses as follows: p gate = q f sw v in , (25) where q = 5 nc and is the charge that is required to turn on the buck switch.
valley current mode control buck converter a4403 12 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com (f) the total losses can now be estimated: p total = p stat + p dyn + p diodecap + p ctrl + p gate . (26) 4. the thermal impedance required for the solution can now be determined: r q ja = . t j ? t a p total (27) note that if a four-layer high thermal efficiency board is used, a thermal impedance of around 30c/w can be achieved. example given selected parameters: v in (min) = 42 v, v out = 3.3 v at 3 a, f sw = 1 mhz, t a = 70c, target junction temperature, t j = 115c, v f = 0.55 v, and c diode = 150 pf, then: (a) switch static losses maximum duty cycle (equation 19): d (max) 0.09 == 3.3 + 0.55 42 + 0.55 r ds(on) of the buck switch (equation 20): r ds(on)tj 350 10 ?3 1 + = 0.535 = ? ? ? ? ? ? ? ? 170 115 ? 25 static loss for each switch (equation 21): p stat = 3 2 0.09 0.535 = 0.433 w (b) switch dynamic losses (equation 22): p dyn 42 0.504 w 5 10 ?9 1000 10 3 1.6 == 2 3 (c) diode capacitance turn-on loss (equation 23): p diodecap 0.132 w = 1 50 10 ?12 42 2 1 10 6 = 2 (d) control losses (equation 24): p ctrl = 0.004 42 = 0.168 w (e) gate charge losses (equation 25): p gate = 5 10 ?9 1 10 6 42 = 0.21 w (f) total losses (equation 26): p total = 0.433 + 0.504 + 0.132 + 0.168 + 0.21 = 1.447 w thermal impedance (equation 27): r q ja 31c/w == 115 ? 70 1.447 for this particular solution, a pcb with high thermal efficency is required to ensure the junction temperature is kept below 115c. for maximum effectiveness, the pcb area underneath the thermal pad of the a4403 should be flooded with copper. several thermal vias (say between 4 and 8) should be used to connect the thermal pad to the internal ground plane. if possible, a further thermal copper plane should be applied to the bottom side of the pcb and connected to the thermal pad of the a4403 through the vias. this calculation assumes no thermal influence from other compo- nents. if possible, it is advisable to mount the recirculation diode (d1) on the reverse side of the printed circuit board. ensure low impedance electrical connections are implemented between board layers. pcb layout guidelines the ground plane is largely dic- tated by the thermal requirements of the previous section. the ground-referenced power components should be referenced to a star ground, located away from the a4403 to minimize ground bounce issues. a small, local, relatively quiet ground plane near the a4403 should be used for the ground-referenced support components, to minimize interference effects of ground noise from the power circuitry. figure 4 illustrates the recommended grounding archi- tecture.
valley current mode control buck converter a4403 13 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com to avoid ground offset issues in the output voltage, it is highly recommended that the ground-referenced feedback resistor r6 should be connected directly to the gnd connection of the a4403. in other words, the r6 ground return should avoid the use of the internal ground plane. all ground-referenced support components (c5 and the dis switch) should also be located as close to the gnd connection as possible. a ?local quiet? ground plane around these components can be implemented; however, this ground plane should have a high impedance connection to the star ground connection of the power stages, as referenced below. the sense resistor connections should be connected in a kelvin circuit (see figure 3) to the corresponding pins on the a4403 (isen and sgnd). note that it is imperative that the pcb traces between the sense resistor pads and the sense connections are as short as possible to minimize the effects of leakage inductance. in noisy systems, it is highly recommended that an r-c filter be used to filter the signal produced across the isen pin. see the sense resistor section and the typical application schematic. if an internal ground plane is used, it is recommended that it does not overlap the switching node, lx, to avoid the possibility of noise pick up. to minimize the possibility of noise injection issues, it is recommended to isolate the ground plane around the high impedance nodes, such as fb and ss. q l r load vin v out d c out c in lx star connection r input voltage figure 5. fet on-cycle current conduction paths q l vin lx star connection d r input voltage r load v out c out c in figure 6. fet off-cycle current conduction paths cin cout d star connection a4403 internal ground plane thermal vias power circuitry a4403 support com p onents local ?quiet? ground plane gnd r r6 switch c5 sgnd figure 4. ground plane configurations
valley current mode control buck converter a4403 14 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com in terms of grounding the power components, a star connection should be made to minimize the ground loop impedances. note that, although a ground plane may be required to meet the ther- mal characteristics of the solution, it is still imperative to imple- ment a star ground connection for the power components. figures 5 and 6 illustrate the importance of keeping the ground connections as short as possible and forming good star connec- tions. figure 5 also illustrates the current conduction paths during the on-cycle of the switching fet. the following points should be noted: ? the capacitor c in should be placed as close as possible to the vin terminal. ? the inductor l should placed as close as possible to the lx terminal and to the output capacitors c out . ? good separation should exist between the lx connection and any adjacent components or traces. figure 6 shows the current conduction path during the off-cycle of the switching fet. the following points should be noted: ? the diode d should be placed as close as possible to both the switching fet and to the inductor. the resistor r should be placed as close as possible to the diode d. ? the boostrap capacitor, c2, and the soft start capacitor, c5, should be located as close as possible to their respective termi- nal connections. the ground reference of the soft start capacitor should be connected as close to the gnd terminal as possible. gnd nc l d1 1 6.3 h lx fb vin 5.0 v 3 a 6.3 v isen sgnd v out a 4403 ton 22 nf r1 100 k c1 2.2 f 100 v 100 m ss dis r3 47 r2 750 r6 3.92 k r5 100 m r4 c2 10 nf c6 47 nf c5 10 f c3 1 nf c7 6.3 v 10 f c4 boot v in 9 to 46 v switching frequency = 1 mhz all capacitors are x5r or x7r ceramic resistors r3 and r4 should be surface mount, low inductance type, rated at 250 mw at 70c figure 7. typical application
valley current mode control buck converter a4403 15 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package eu, 16-contact qfn for the latest version of this document, visit our website: www.allegromicro.com copyright ?2008-2013, allegro microsystems, llc allegro microsystems, llc reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions a s may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, llc assumes n o re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. 0.95 c seating plane c 0.08 17x 16 16 2 1 1 2 16 2 1 a a terminal #1 mark area coplanarity includes exposed thermal pad and terminals b exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) for reference only (reference jedec mo-220wggc) dimensions in millimeters exact case and lead configuration at supplier discretion within limits shown c d d c reference land pattern layout (reference ipc7351 qfn65p400x400x80-17w2m) all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) 4.10 0.35 0.65 4.10 0.65 0.75 0.05 0.30 0.05 0.40 0.10 2.70 2.70 4.00 0.15 4.00 0.15 2.70 2.70 b pcb layout reference view

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